Wednesday, 8 October 2014

This is a Proteus tutorial to construct SR flip-flop using nand gate. Here 2 nand gates are used.
If we use the SR logic then the output in front of R is considered as Q and the output in front of S is considered as Q'.
If we use the RS logic then the output in front of S is considered as Q and the output in front of R is considered as Q'.
using Proteus, after you construct SR flip-flop, you can verify the table of SR flip-flop

4 bit full adder

This video is the full application of the function of creating substructure in Proteus.
Here the substructure of a single bit full adder is prepared and its carry is given as the third input to next single bit full adder by following this you can prepare n bit full adder.
Here 4 bit full adder is prepared. In this the sum at all respective adders is shown in output and the last carry is also shown.
Here you may also construct the the full adder substructure using the two half adder substructures in it.